»RISC-V Privileged Architecture«
2018-10-14, 13:15–13:45, Amph. A
In this talk we will present the privileged modes of operation of a typical RISC-V core regarding various use cases, and the features that are implemented for each one.
RISC-V is an open and free Instruction Set Architecture (ISA) designed at UC Berkeley. ISAs serve as the interface between software and hardware. While a processor core usually spends most of its time executing application code in user-mode, the management of the machine and the handling of critical events is performed at a higher privilege level. In this talk we will present the high-level design of RISC-V privileged architecture. RISC-V defines two higher privilege modes: (i) the machine mode which executes the most trusted code, and (ii) the supervisor mode which provides support for Unix-like operating systems. We will discuss essential features that are implemented for each privileged mode such as memory protection, virtual memory, interrupts, etc. These features can be used as building blocks for the design of a variety of computing systems, ranging from minimal embedded systems up to custom designed servers. The open nature of RISC-V will play a decisive role in the future, as Moore’s law fades and custom-core designs rise in importance.